Multidrain NMOS for VLSI logic design
Abstract
A multidrain NMOS circuit configuration (MD) is investigated, and its advantages over the conventional pull-up pull-down (PUD) configuration are discussed. Among them are efficient use of silicon area, less sensitivity to interconnections, shorter delay times, a controlled value of logic swing which is independent of V sub DD, and the possibility of integrating into a stacked structure where the load does not consume silicon real estate. The MD and the PUD configurations are compatible, the latter being used where a large fan-out is required.
- Publication:
-
IEEE Transactions on Electron Devices
- Pub Date:
- April 1982
- DOI:
- 10.1109/T-ED.1982.20777
- Bibcode:
- 1982ITED...29..779E
- Keywords:
-
- Integrated Circuits;
- Logic Design;
- Metal Oxide Semiconductors;
- Very Large Scale Integration;
- Circuit Diagrams;
- Efficiency;
- Gates (Circuits);
- Silicon Junctions;
- Electronics and Electrical Engineering