Self-aligned transistor with sidewall base electrode

A multiple self-aligned structure that facilitates high packing density and high speed in bipolar VLST's is proposed. The device has polysilicon sidewall base electrodes to reduce parasitic junction capacitances. The new devices indicate that capacitances between the base and collector regions are reduced to 1/4 and the ratio of reverse-to-forward current gain is increased about 5 times that of conventional bipolar transistor structures, and gate delay in IIL circuits is about 1 ns/gate. The structure opens the way for further scaled-down VLSI.