Minimum propagation delays in VLSI
Abstract
It is demonstrated that propagation delays can be achieved in VLSI circuits that are logarithmic in the lengths of the wires, provided the connection pattern is designed to meet certain constraints. These constraints are satisfied only by connection patterns having a hierarchical structure. It is also shown that even at the ultimate physical limits of the technology, the propagation for reasonably sized VLSI chips is dominated by these considerations rather than by the velocity of light.
- Publication:
-
IEEE Journal of Solid-State Circuits
- Pub Date:
- August 1982
- DOI:
- 10.1109/JSSC.1982.1051810
- Bibcode:
- 1982IJSSC..17..773M
- Keywords:
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- Chips (Electronics);
- Very Large Scale Integration;
- Constraints;
- Light Speed;
- Time Lag;
- Electronics and Electrical Engineering