High-speed low-power silicon MESFET parallel multipliers
Abstract
The design of fast, low-power silicon MESFET parallel multipliers is studied. The architecture of the multipliers and the designs of the functional blocks are discussed. The overall performance of the multipliers is estimated from the simulated performances of the functional blocks and from system simulations with a logic simulator. The actual performance of 8 x 8 and 10 x 10 bit TTL-compatible multipliers, fabricated with a 2.5-micron silicon MESFET technology (1.5-2-micron effective dimensions) is compared to the simulations.
- Publication:
-
IEEE Journal of Solid-State Circuits
- Pub Date:
- February 1982
- DOI:
- 10.1109/JSSC.1982.1051688
- Bibcode:
- 1982IJSSC..17...69H
- Keywords:
-
- Field Effect Transistors;
- Multipliers;
- Parallel Processing (Computers);
- Schottky Diodes;
- Signal Processing;
- Systems Simulation;
- Digital Systems;
- Energy Dissipation;
- Fabrication;
- Metal Surfaces;
- Performance Prediction;
- Power Conditioning;
- Silicon Transistors;
- Time Lag;
- Ttl Integrated Circuits;
- Electronics and Electrical Engineering