VLSI design for concurrent test
Abstract
This paper examines the questions of VLSI chip complexity from two points of view: (1) the relationship between gate complexity and the realization of generic system functions on a single chip, and (2) the realism of on-chip redundancy and self test within the gate complexity trends. The paper attempts to gain insight into the following questions. How can untestable levels of complexity be dealt with. What is the relationship between system-on-a-chip architecture and test ability. Are new concepts and architectures needed when the circuit becomes the system. The paper concludes that the use of on-chip concurrent test procedures are necessary and that error control coding is the key to success. The concepts are illustrated.
- Publication:
-
4th Digital Avionics Systems Conference
- Pub Date:
- 1981
- Bibcode:
- 1981davs.conf..556H
- Keywords:
-
- Avionics;
- Chips (Electronics);
- Electronic Equipment Tests;
- Large Scale Integration;
- Military Technology;
- Network Synthesis;
- Channels (Data Transmission);
- Data Processing;
- Gates (Circuits);
- Performance Tests;
- Redundant Components;
- Self Tests;
- Technology Assessment;
- Electronics and Electrical Engineering