Estimation of confidence limits for testing large logic networks
Abstract
This report describes a methodology and means for accurately determining confidence limits for the reliability of large digital networks, without exhaustively exercising all possible input sequences or simulating all logic faults in the network. The report is divided into two parts. In the first part, some mathematical models to estimate the reliability of digital circuits are presented. A heuristic method of assigning weights to faults depending on their 'importance' in a given circuit is described. The models presented can be used to: (1) predict the reliability of a circuit, (2) evaluate test sequences and (3) develop more accurate reliability models of (redundant) fault tolerant computers. The second part of the report deals with the statistical methods of estimating confidence limits.
 Publication:

Final Report Southern Methodist Univ
 Pub Date:
 May 1980
 Bibcode:
 1980smu..rept.....F
 Keywords:

 Confidence Limits;
 Estimating;
 Integrated Circuits;
 Mathematical Models;
 Prediction Analysis Techniques;
 Circuits;
 Error Detection Codes;
 Heuristic Methods;
 Probability Density Functions;
 Statistical Analysis;
 Electronics and Electrical Engineering