The gated-access MNOS memory transistor
Abstract
A new modification of the MNOS transistor results in significant advantages. It combines a depletion-mode channel with electrically separate electrodes over the memory portion and the fixed threshold portion of a step-gate device. This eliminates read disturb during interrogation; therefore, much longer retention is now possible. It also decreases access time within an LSI array. For block-written EAROM's, a new form of dynamic inhibit makes memory array isolation unnecessary. These and other improvements obtained with this structure do not require new processes or a significant increase in size.
- Publication:
-
IEEE Transactions on Electron Devices
- Pub Date:
- January 1980
- DOI:
- 10.1109/T-ED.1980.19849
- Bibcode:
- 1980ITED...27..266W
- Keywords:
-
- Computer Storage Devices;
- Metal-Nitride-Oxide-Semiconductors;
- Network Synthesis;
- Transistor Circuits;
- Block Diagrams;
- Electrodes;
- Gates (Circuits);
- Large Scale Integration;
- Read-Only Memory Devices;
- Volt-Ampere Characteristics;
- Electronics and Electrical Engineering