Improving the performance of GaAs integrated logic circuits in anticipation of large scale integration

A computerized simulation of performance and structural parameters for field effect transistors in logic circuits was performed in order to optimize power consumption for diode transistor logic designs. Based on reports from the literature, logic circuits on GaAs generally show an energy dissipation of approximately 20 mW/gate for a limit of 10 gates per integrated circuit. An extensive description of the models used in these simulations is given and, after optimization, best results give a power consumption of 0.05 mW/gate for integrated circuits of from 100 to 1000 gates.