Noncoplanar high power FET
Abstract
Using a p- substrate as the gate and employing low-doped V-grooves under the source and drain to reduce parasitic capacitances, a noncoplanar power FET was designed and fabricated which achieved submicron gate lengths with photolithopraphy masks employing a resolution limit of several microns. Device performance was limited by low values of pinch-off voltage and gate breakdown voltage. Ion implantation or diffusion should enable the breakdown voltage to be raised by virtue of separating the p-n junction from the growth interface.
- Publication:
-
NASA STI/Recon Technical Report N
- Pub Date:
- December 1979
- Bibcode:
- 1979STIN...8027607B
- Keywords:
-
- Field Effect Transistors;
- Ion Implantation;
- Semiconductor Junctions;
- Gallium Arsenides;
- P-N Junctions;
- Semiconductor Devices;
- Electronics and Electrical Engineering