Placement and routing algorithms for hierarchical integrated circuit layout

Algorithms for the automatic layout of custom integrated circuits were developed. These algorithms are suitable for the design of very large scale integrated circuits. Hierarchical decomposition is used to reduce the circuit complexity to the level that it can be comprehended by the designer. At each level of the hierarchy, the layout problem consists of the placement and interconnection of rectangular blocks of arbitrary size and shape. The layout is modelled using graph theoretical methods. The problem is broken down into two major sub-problems: placement and routing. Placement consists of a constructive initial placement followed by iterative improvement. The interconnection or routing process first finds a general layout topology for the interconnection nets and then a detailed routing using constructive and iterative improvement methods. The algorithm minimizes layout area and assures 100% routing completion.