New input/output designs for high speed static CMOS RAM
Abstract
New input and output schematics and optimum design for cell and array are proposed, and applied to a 256 x 4 bit CMOS static RAM. Simplified decoder circuit with effective decoder control circuit has a high speed and a wide timing margin. Simple sense amplifier and compact output circuit bring higher speed and reduction in pattern area. Using p-channel transfer gate for memory cell and array, the switching speed and operational stability are much improved. The device is fabricated by 5-micron layout-rule Si-gate CMOS technology. An 80 ns access time and 100 ns minimum cycle time are acquired at 5 V supply. Power dissipation is less than 7.5 mW at 1 MHz operation.
- Publication:
-
IEEE Journal of Solid-State Circuits
- Pub Date:
- October 1979
- DOI:
- 10.1109/JSSC.1979.1051278
- Bibcode:
- 1979IJSSC..14..823A
- Keywords:
-
- Cmos;
- Decoding;
- Logic Circuits;
- Network Synthesis;
- Random Access Memory;
- Access Time;
- Energy Dissipation;
- Gates (Circuits);
- Input/Output Routines;
- N-Type Semiconductors;
- P-Type Semiconductors;
- Packing Density;
- Signal To Noise Ratios;
- Volt-Ampere Characteristics;
- Electronics and Electrical Engineering