Charge-splitting c.c.d. tapped delay lines
Abstract
Two new CCD tapped-delay line structures are described that overcome the disadvantages of floating-gate tapping by separating the charge transfer and sensing functions. In one structure (parallel-channel tapping), 32-bit tapped delay lines are constructed by fabricating 32 separate parallel CCDs from 1 to 32 bits long, having common inputs, common transfer electrodes and separate output amplifiers, each channel being separated from the next by a channel stop diffusion. This results in a device that gives equal tap weights at the output, but local dark-current variations could give rise to differential offsets between channels. The second structure uses the concept of partitioning, by means of a channel stop wedge, successive small fractions of the total input charge packet, each charge split being delayed from the previous split by one bit. This allows the device to be programmable at mask level by the correct positioning of the partitioning wedges. Both types of device are constructed to be p-i-n compatible and can be operated interchangeably. High performance is achieved.
- Publication:
-
Electronics Letters
- Pub Date:
- March 1979
- DOI:
- 10.1049/el:19790143
- Bibcode:
- 1979ElL....15..204H
- Keywords:
-
- Charge Coupled Devices;
- Delay Lines;
- Signal Processing;
- Amplifiers;
- Photomicrographs;
- Electronics and Electrical Engineering