Use of inhibition for implementing logic functions with NAND, NOR, and EXOR gates
Abstract
A graphical procedure of inhibition is used to obtain a general method of writing a disjunctive logic function as a modulo-2 sum and to deduce algebraically from this form all the other nonredundant modulo-2 sums. Among these sums are the Reed-Muller canonical forms and the forms requiring a minimum number of NAND and NOR gates for imple
- Publication:
-
L'Onde Electrique
- Pub Date:
- July 1978
- Bibcode:
- 1978LOEle..58..488L
- Keywords:
-
- Gates (Circuits);
- Inhibition;
- Logic Circuits;
- Optimization;
- Boolean Functions;
- Canonical Forms;
- Switching Circuits;
- Electronics and Electrical Engineering