4-micron LSI on SOS using Coplanar-II process
Abstract
SOS Si-gate 4-micron NMOS devices using the Coplanar-II process have been investigated for the purpose of improving the power-delay product and realiability of SOS LSI. By using the Coplanar-II process to fabricate SOS devices, the gate breakdown field is improved by more than a factor of 2 (8.7 MV/c) over transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents formed by use of the conventional SOS device fabrication process are suppressed. A typical drain current of 7 x 10 to the -11th A/8 microns is obtained.
- Publication:
-
IEEE Transactions on Electron Devices
- Pub Date:
- August 1978
- DOI:
- 10.1109/T-ED.1978.19206
- Bibcode:
- 1978ITED...25..945M
- Keywords:
-
- Circuit Reliability;
- Fabrication;
- Large Scale Integration;
- Metal Oxide Semiconductors;
- Sos (Semiconductors);
- Thin Films;
- Coplanarity;
- Electrical Faults;
- Planar Structures;
- Production Engineering;
- Reliability Engineering;
- Time Lag;
- Electronics and Electrical Engineering