Ion implantation of neon in silicon for planar amorphous isolation
Abstract
A new planar isolation technique for silicon integrated circuits is presented. The process uses neon implantation to create high-resistivity regions of amorphous silicon between active devices on a common substrate. Excellent surface planarity is obtained, and no high-temperature processing is required. Results on test devices and an amorphous isolated m.n.o.s. capacitor memory are described.
- Publication:
-
Electronics Letters
- Pub Date:
- July 1978
- DOI:
- 10.1049/el:19780310
- Bibcode:
- 1978ElL....14..460Y
- Keywords:
-
- Amorphous Semiconductors;
- Integrated Circuits;
- Ion Implantation;
- Metal-Nitride-Oxide-Silicon;
- Neon;
- Amorphous Silicon;
- Electrical Resistivity;
- Planar Structures;
- Silicon Junctions;
- Substrates;
- Volt-Ampere Characteristics;
- Electronics and Electrical Engineering