Investigations concerning limit cycles in digital filters

The reported investigations are concerned with limit cycles in recursive digital filters. The limit cycles considered can occur in connection with nonlinear operations which are needed for a reduction of word length in fixed-point arithmetic. It is assumed that the fundamental structure of a higher-order digital filter is based on cascade of parallel circuits of blocks of the 2nd degree. Formulas for estimating the amplitude and period length of limit cycles in the case of blocks of the 2nd degree in the 1st and 2nd canonical form at disappearing input signal are compared with experimentally determined data. The method of 'effective coefficients' is used for the theoretical interpretation of the various types of limit cycles and their characteristics. Approaches are discussed for the suppression of limit cycles. An investigation is conducted regarding the effects of additive noise in the input signal.