Design of direct frequency synthesizers
Abstract
It is shown that a rate multiplier or a binary adder can be used to successfully fulfill these requirements if a frequency division is first performed on their outputs to reduce the phase jitter common to such devices. The phase jitter is described in the time domain, via algorithms, for both the rate multiplier and the binary adder; using computer analysis, it was found that this jitter decreased directly as the divisor increased. It is shown that the frequency domain phase noise also decreased directly as the divisor increased, and that the frequency domain phase noise over a limited bandwidth is directly proportional to the time domain jitter.
- Publication:
-
Ph.D. Thesis
- Pub Date:
- 1976
- Bibcode:
- 1976PhDT........79W
- Keywords:
-
- Algorithms;
- Frequency Synthesizers;
- Systems Engineering;
- Time Lag;
- Computer Programs;
- Frequency Converters;
- Low Frequencies;
- Low Noise;
- Electronics and Electrical Engineering