An architecture for digital signal processors

An architecture for the machine organization of digital signal processors is proposed, that is based on a representation of the processing coefficients, derived from the canonical signed digit code. This leads to a realization requiring a minimum number of add/subtract operations to implement the required multiplications and additions. The proposed organization, while general in structure, will allow each application to achieve its best possible throughput rate. Mixing of coefficients with various word-lengths is straightforward, and a computational advantage is realized from shorter word-lengths. Finally the proposed organization is shown to be highly modular and well suited to integrated circuit implementation, and offer a more efficient implementation in terms of achieved computing power per hardware expenditure.