Processor implemented decoders for block and convolutional codes

This paper describes several error control coding techniques for both block and convolutional codes which have been implemented in three processors. The emphasis of the work is on practical encoding/decoding techniques which can be implemented together with the appropriate modems on a processor in real time. Bit interleaving of a BCH code and a generalized burst trapping technique using BCH codes are discussed for an HF application. A short constraint length convolutional code/Viterbi decoder and a long constraint length convolutional code/ZJ stack decoder are presented for a satellite and ELF application, respectively. Decoder storage requirements are specified and possible operating data rates are given.