Graphene-based interconnects: Electrical performance and reliability

According to the ITRS Roadmap, on-chip interconnects wire width and current density will reach 22 nm and 5.8x106 A/cm2 in 2020, respectively. The electrical resistivity of Cu increases with scaled critical dimensions due to exacerbated carrier scattering at grain boundaries and interfaces, resulting in signal speed degradation. Electronmigration (EM)-related failure due to intensified current distribution posts extra limits to ultra-scaled systems. Innovative interconnect solutions are needed to tackle performance and scaling challenges. In recent years, low-dimensional carbon nanostructures have been intensively studied for potential interconnect applications due to their excellent immunity to electromigration and superior mechanical, electrical and thermal properties. Graphene (single layer or a few layers of carbon atoms arranged in a 2-D honeycomb lattice) has attracted considerable attention since its discovery in 2004. Unique properties have been observed in graphene, including linear E-k dispersion, ballistic transport, ultra-high carrier mobility (200,000cm2/V-s), and exceptional thermal conductivity (4800W/m-K). For interconnect application, graphene is predicted to outperform Cu at ultra-scaled line width (below 8 nm). Experimentally, graphene nanoribbon (GNR) patterned by photolithography has been proved to exhibit resistivity comparable to Cu (wire width: from 18 nm to 39 nm) and the maximum current-carrying capacity up to 108 A/cm2. It is conceivable that local interconnects made by graphene (owing to its superior electrical behavior at sub-10nm wire dimensions and the "natural' interface with graphene-based devices, e.g., FET) in combination with the well-established Cu-based global interconnects (more conductive than graphene at larger wire dimensions) would be the ideal integration strategy, leading to the hybrid interconnect system implementation. However, to-date very little experimental evidence has been reported on the characteristics of graphene for interconnect design purpose. In this thesis, we will investigate key factors including reliability, scalability, compatibility and electrical performance in the envisioned BLG/Cu hybrid system. The work of this thesis mainly includes the following research projects: (1) Investigation of the reliability limiting factors of graphene/copper hybrid interconnect system by examining its current-induced breakdown behavior and graphene/copper contact (2) Demonstration of doping in graphene by applying local electrical stressing. Additionally, electrical stressing induced graphene p-n junction was experimentally studied and analyzed (3) Study of large-area and less defective graphene CVD growth and transfer techniques (4) Demonstration of 3D stacked multilayer graphene (s-MLG) as the potential candidate for future carbon-based interconnects.