3D IC TSV-Based Technology: Stress Assessment For Chip Performance
Abstract
Potential challenges with managing mechanical stress distributions and the consequent effects on device performance for advanced 3D through-silicon-via (TSV) based technologies are outlined. A set of physics-based compact models of a multi-scale simulation flow for assessment of the mechanical stress across the device layers in the silicon chips stacked and packaged with the 3D TSV technology is proposed. A calibration technique based on fitting to measured transistor electrical characteristics of a custom designed test-chip is proposed.
- Publication:
-
Stress-Induced Phenomena in Metallization: 11th International Workshop
- Pub Date:
- November 2010
- DOI:
- 10.1063/1.3527127
- Bibcode:
- 2010AIPC.1300..202S
- Keywords:
-
- stress analysis;
- transistor circuits;
- finite difference methods;
- hole mobility;
- doping profiles;
- 62.40.+i;
- 85.30.Pq;
- 47.11.Bc;
- 72.20.Ee;
- 85.40.Ry;
- Anelasticity internal friction stress relaxation and mechanical resonances;
- Bipolar transistors;
- Finite difference methods;
- Mobility edges;
- hopping transport;
- Impurity doping diffusion and ion implantation technology