VHDL implementation of a communication interface for ingrated MEMS

The main objective of this paper is to develop a distributed architecture for integrating MEMS based on a hierarchical communications system governed by a master node. A micro-electromechanical system (MEMS) integrates a sensor with its signal conditioner and communications interface, thus reducing mass, volume and power consumption. In pursuing this objective, we have developed an Intellectual Propriety (IP) model with VHSIC Hardware Description Language (VHDL) for the bus interface that can be easily added to the micro-system. The connection between the MEMS incorporating this module and the sensor network is straightforward. The core thus developed contains an Interface File System (IFS) that supplies all the information related to the microsystem that we wish to connect to the net, allowing the specific characteristics to be isolated to the micro-instrument. This allows all the nodes to have the same interface. In order to support complexity management and composability, there are a real-time service interface and a not timecritical configuration interface. So the design includes a new node integration VHDL module. The design has been implemented in a Field Programmable Gate Array (FPGA) and was successfully tested. The FPGA implementation makes the designed nodes small-size, flexible, customizable, reconfigurable and reprogrammable with advantages of well-customized, cost-effective, integration, accessibility and expandability. The VHDL hardware solution is a key feature for size reduction. The system can be resized according to its needs taking advantages of the VHDL configurability.