A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%
Abstract
- Publication:
-
IEEE Journal of Solid-State Circuits
- Pub Date:
- March 2001
- DOI:
- 10.1109/4.910489
- Bibcode:
- 2001IJSSC..36..503Y