Scalable Quantum Error Correction for Surface Codes using FPGA
Abstract
A faulttolerant quantum computer must decode and correct errors faster than they appear. The faster errors can be corrected, the more time the computer can do useful work. The UnionFind (UF) decoder is promising with an average time complexity slightly higher than $O(d^3)$. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGAbased implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to $d$, given $O(d^3)$ parallel computing resources. The decoding time per measurement round decreases as $d$ increases, a first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid treegrid structure. We are able to implement $d$ up to 21 with a Xilinx VCU129 FPGA, for which an average decoding time is 11.5 ns per measurement round under phenomenological noise of 0.1\%, significantly faster than any existing decoder implementation. Since the decoding time per measurement round of Helios decreases with $d$, Helios can decode a surface code of arbitrarily large $d$ without a growing backlog.
 Publication:

arXiv eprints
 Pub Date:
 January 2023
 DOI:
 10.48550/arXiv.2301.08419
 arXiv:
 arXiv:2301.08419
 Bibcode:
 2023arXiv230108419L
 Keywords:

 Quantum Physics;
 Computer Science  Hardware Architecture