HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation
Abstract
To speedup Deep Neural Networks (DNN) accelerator design and enable effective implementation, we propose HybridDNN, a framework for building high-performance hybrid DNN accelerators and delivering FPGA-based hardware implementations. Novel techniques include a highly flexible and scalable architecture with a hybrid Spatial/Winograd convolution (CONV) Processing Engine (PE), a comprehensive design space exploration tool, and a complete design flow to fully support accelerator design and implementation. Experimental results show that the accelerators generated by HybridDNN can deliver 3375.7 and 83.3 GOPS on a high-end FPGA (VU9P) and an embedded FPGA (PYNQ-Z1), respectively, which achieve a 1.8x higher performance improvement compared to the state-of-art accelerator designs. This demonstrates that HybridDNN is flexible and scalable and can target both cloud and embedded hardware platforms with vastly different resource constraints.
- Publication:
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arXiv e-prints
- Pub Date:
- April 2020
- DOI:
- 10.48550/arXiv.2004.03804
- arXiv:
- arXiv:2004.03804
- Bibcode:
- 2020arXiv200403804Y
- Keywords:
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- Computer Science - Hardware Architecture;
- Computer Science - Computer Vision and Pattern Recognition
- E-Print:
- Published as a conference paper at Design Automation Conference 2020 (DAC'20)