Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications
Abstract
We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around (GAA) FET devices as promising candidates to obtain a better power-performance metric for logic applications for advanced sub-5 nm technology nodes, in comparison to finFETs. In addition, vertical NW/NS GAA FETs appear particularly attractive for enabling highly dense memory cells such as SRAMs (with improved read and write stability), and as the selector devices for ultra-scaled MRAMs with lower energy consumption values. These cells can be manufactured by a cost-effective, co-integration scheme with a triple-gate finFET or a lateral NW/NS GAA FET high-performance logic platform for increased on-chip memory content.
- Publication:
-
Solid State Electronics
- Pub Date:
- June 2020
- DOI:
- 10.1016/j.sse.2019.107736
- Bibcode:
- 2020SSEle.16807736V
- Keywords:
-
- Lateral and vertical nanowire and nanosheet gate-all-around FETs;
- Scaling;
- Logic;
- Memory;
- CMOS;
- MRAM