Synthesis of video processing with open-source hardware descriptor languages

Technology development has allowed each day we have devices that can contain all the functionality of a Digital System on a single chip (SoC) and they have a very high scale of integration (VLSI) hundreds of millions of gates at very low costs. As well as the design, verification and synthesis tools offered by the development factories those make these SoC and FPGA components. This companies offer Integrated Development Environments with software tools to perform from the specification of the Design to its synthesis in C.I. and its verification in industry standard languages as Verilog and VHDL. This paper shows the advantages in design, verification, synthesis and testing that can be obtained by using HDL languages such as CHISEL, MyHDL for the processing of video processing in Real-Times and demonstrate its main advantages in both learning time and costs.