Characterization of an architecture for front-end pixel binning in an integrating pixel array detector
Optimization of an area detector involves compromises between various parameters like frame rate, read noise, dynamic range and pixel size. We have implemented and tested a novel front-end binning design in a photon-integrating hybrid pixel array detector using the MM-PAD-2.0 pixel architecture. In this architecture, the pixels can be optionally binned in a 2×2 pixel configuration using a network of switches to selectively direct the output of 4 sensor pixels to a single amplifier input. Doing this allows a trade-off between frame rate and spatial resolution. Tests show that the binned pixels perform well, but with some degradation on performance as compared to an un-binned pixel. The increased parasitic input capacitance does reduce the signal collected per x-ray as well as increases the noise of the pixel. The increase in noise is, however, less than the factor of 2 increase one would observe for binning in post-processing. Spatial scans across the binned pixels show that no measured signal intensity is lost at the inner binning unit boundaries. In the high flux regime, at a 2×2 pixel wide beam spot (FWHM) size, binned mode responds linearly up to a photon flux of 107 x-rays/s, and performs comparably with un-binned mode up to a photon flux of 108 x-rays/s. While this study demonstrates a proof of concept for front-end binning in integrating detectors, we also identify changes to this early-stage prototype which can further improve the performance of binning pixel structures.