Design of communication between FPGA and microcontroller for experimental imager LAPAN-A4

The fourth generation of LAPAN satellite will employ Experimental LAPAN Line Imager for Space Application (ELLISA) for its mission on earth observation. In developing the imager, embedded systems like microcontroller and FPGA (field-programmable gate array) are utilized as interface and timing control, respectively. FPGA controls CCD (charge-coupled device) and ADC (analog-to-digital converter) timings and alters the data from CCD format to Camera Link format. Microcontroller, as an interface, handles command from users and other subsystems. Communication system is established between the two devices in order to transfer and translate incoming data from/to the subsystems and user. In this paper, a customized communication design has been successfully implemented between the microcontroller and FPGA for ELLISA development. This communication design can be realized on microcontroller with simple features.