Write Scheme Allowing Reduced LRS Nonlinearity Requirement in a 3D-RRAM Array With Selector-Less 1TNR Architecture
Abstract
- Publication:
-
IEEE Electron Device Letters
- Pub Date:
- February 2014
- DOI:
- 10.1109/LED.2013.2294809
- Bibcode:
- 2014IEDL...35..223C