Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the CMOS roadmap. Structure and operational principles of these devices are described. Theories used for benchmarking these devices are overviewed, and a general methodology is described for consistent estimates of the circuit area, switching time and energy. The results of the comparison of the NRI logic devices using these benchmarks are presented.
- Pub Date:
- February 2013
- Condensed Matter - Mesoscale and Nanoscale Physics
- 91 pages, 67 figures, 11 tables. Related to the conference presentation D. Nikonov and I. Young, Uniform Methodology for Benchmarking Beyond-CMOS Logic Devices, Proceedings of IEDM, 25.4 (2012)