Electromigration data and a theoretical model have shown that Cu lifetime in on-chip Damascene interconnect structures has dropped for every new interconnect generation, even when tested at the same current density. In addition, a mixture of bamboo and polycrystalline grain structures instead of a bamboo-like structure observed for <90 nm wide lines (65 nm technology node) resulted in further lifetime degradation by the addition of grain boundary diffusion. The techniques for improving EM lifetime either by modifying the interconnect structure by adding dummy vias on top of a Cu line, a Ru cap on the Cu top surface, or the formation of a thin CuSiN layer at the Cu/dielectric interface were investigated. The upper dummy vias, the Ru cap or CuSiN layer on the top surface of the Cu lines interrupted the Cu mass flow along the top surface interface which can improve lifetimes. The upper level dummy via structure was a powerful tool for helping to understand the Cu microstructure and to distinguish fast diffusion paths in the line.
Stress-Induced Phenomena in Metallization: Tenth International Workshop on Stress-Induced Phenomena in Metallization
- Pub Date:
- June 2009
- Electronic transport in nanoscale materials and structures;
- Nondestructive testing: electromagnetic testing eddy-current testing