Study of the extrinsic parasitics in nano-scale transistors

We investigate the extrinsic parasitics in symmetric ultra-thin body double-gate (SUTBDG) devices with raised source/drain (S/D). An analytical model for the fringing capacitance is derived by using dual conformal mapping and proven accurate by two-dimensional (2D) device simulation. From the fringing capacitance, we project an aggressive scaling in gate height as gate length shrinks, in order to maintain a roughly constant fraction of the fringing capacitance to the total gate capacitance in sub-20 nm transistors. Convenient analytical models for the extrinsic series resistances are also derived and validated by simulation. For a raised S/D structure with a wrapped contact and contact resistivity as good as 1 × 10^-8 Ω cm², we find that the heavily doped thin-body region contributes the greatest part of the extrinsic series resistance, followed by the resistance of the contacted region and the spreading resistance. For a non-raised S/D with a wrapped contact, we find that the resistance of the contacted region is dominant. Our device simulation results suggest that optimal spacer thicknesses depend on the trade-off between fringing capacitance and series resistance.