Analysis of the thin-film SOI lateral bipolar transistor and optimization of its output characteristics for high-temperature applications
In this paper, we investigate and optimize the static characteristics of NPN lateral bipolar transistors implemented in a thin-film fully-depleted SOI CMOS process for high-temperature analog applications. The basic lateral SOI bipolar device, which shows good behaviour in high-temperature circuits in spite of its relatively poor performances, is firstly described regarding its process and layout parameters. Then the concept of the graded-base bipolar transistor is introduced. This device presents significantly improved output characteristics while preserving standard current gain and CMOS process compatibility. Measurements and simulations are used to demonstrate the improvements of the breakdown voltage and the Early voltage of the bipolar device.