Low Schottky barrier source/drain for advanced MOS architecture: device design and material considerations
Abstract
An alternative MOSFET architecture based on the use of low barrier Schottky source/drain (S/D) contacts coupled to a thin silicon-on-insulator (SOI) film is described. Two-dimensional device simulations are used to demonstrate the advantage of low Schottky barrier S/D over conventional implanted technologies in terms of current drive capabilities. It is shown that the silicide penetration in the silicon does not increase the contact resistance for this structure while a severe degradation of the current drive is observed for conventional MOS architectures. Experiments conducted on Pt/Ge metallic stacks on p-type silicon show that very low Schottky barriers to hole can be obtained (∼50 meV).
- Publication:
-
Solid State Electronics
- Pub Date:
- July 2002
- DOI:
- 10.1016/S0038-1101(02)00033-3
- Bibcode:
- 2002SSEle..46..997D