Changes in carrier profiles of bonded SOI wafers with thermal annealing measured by the spreading resistance method

Carrier concentration profiles of both p-type and n-type bonded silicon-on-insulator (SOI) wafers are measured using spreading resistance analysis. A high-resistivity region is observed near the SOI/buried oxide (BOX) interface for the as-received wafers, irrespective of the conduction type. After the high-temperature annealing at about 1000 °C, the high-resistivity region disappears, and the interface region is inverted in p-type SOI and accumulated in n-type SOI. To interpret the results, carrier concentration profiles are theoretically calculated considering a fixed charge in the BOX and electronic states at the SOI/BOX interface. From comparison between the experimental and theoretical results, it is concluded that the SOI/BOX interfaces initially have interface state density of the order of 10 ¹¹ cm ^-2 eV ^-1, which is decreased to the order of 10 ¹⁰ cm ^-2 eV ^-1 by the annealing.