Implementing area-optimized narrowband FIR filters using Xilinx FPGAs

This paper describes the implementation of very high- performance narrow-band finite impulse response (FIR) filters using Xilinx field programmable gate arrays (FPGAs). Multirate as well as single rate architectures are considered. By exploiting the narrow-band nature of the filtering process, a very area-efficient FPGA filter mechanization referred to as an interpolated FIR (IFIR) filter is developed. Several design examples are presented. A lowpass single rate IFIR consumes only 47.9% of the logic requirements in comparison to other area efficient FPGA FIR structures that have been reported in the literature. Multirate implementations provide larger logic savings. A 50-to-1 decimator is presented that uses only 13.7% of the logic resources of a standard FPGA polyphase implementation.