Quantum Gates, Mixed-State Entanglement and Error - Codes.

I give an overview of quantum information and existing results. I present a new view of of locality and argue that the criterion for nonlocality of a mixed state M is non-zero E(M), the entanglement required to prepare M by local actions. I compare E(M) with the amounts D_1(M) and D_2(M) that can be locally distilled from M by entanglement purification protocols (EPPs) using one- and two-way classical communication respectively, and give an exact expression for E(M) when M is Bell-diagonal. I show the relationship between EPPs and quantum error-correcting codes (QECCs). In an EPP perfectly entangled pure states are extracted with yield D from bipartite mixed states M; in a QECC arbitrary quantum states are reliably transmitted at rate Q through a noisy channel chi. I prove an EPP involving one-way classical communication and acting on mixed state M(chi) (obtained by sharing EPR pairs through chi) yields a QECC on chi with rate Q = D, and vice versa. While EPPs require classical communication, QECCs do not; I prove Q is not increased by adding one-way classical communication. However, both D and Q can be increased by adding two-way communication. I show that certain noisy channels can be used for reliable quantum transmission iff two-way communication is available. I exhibit a family of codes based on universal hashing able to achieve an asymptotic Q (or D) of 1-S for independent noise models, where S is the error entropy. I obtain a 5-bit single-error-correcting quantum block code. I prove that iff a QECC results in high fidelity for the case of no error the QECC can be recast with the encoder as the matrix inverse of the decoder. I discuss quantum gate arrays for quantum computation and present numerical results indicating that six two-bit quantum gates are enough to implement any three-bit quantum gate, and results for implementing specific gates. An analytic argument and numerical results are given for why a two-bit gate adds nine, twelve, fifteen, or zero parameters to the space accessible by a gate array, depending on the topology.