Processing Physics in Silicon-On Material

Silicon-on-Insulator (SOI) material has received significant attention from the integrated circuits industry for both niche and large volume CMOS logic and DRAM applications. In this work, the physics of processing in the silicon-on -insulator material system is investigated rather than SOI device physics. This study focuses on the thermal processing of bulk and SOI material. The motion of dopants in bulk, single-implant SIMOX (Separation by IMplantation of OXygen), multiple-implant SIMOX, and BESOI (Bonded and Etched back Silicon On Insulator) material during oxidation, nitridation, and post-implantation annealing was studied and modeled. A significant reduction in the enhanced dopant diffusion due to interstitial supersaturation was observed in the SOI samples relative to bulk samples. This phenomenon has been modeled by taking into account the interactions of excess interstitials and the buried Si-SiO_2 interface in the SOI material. An effective interstitial recombination velocity was extracted for the buried Si -SiO_2 interface for each SOI material type. The higher effective interstitial recombination velocity in the SIMOX material was correlated with increased interfacial surface roughness measured by atomic force microscopy. This study also demonstrated that the magnitude of dopant motion during post-implantation annealing is higher for low temperatures such as 800^ circC than high temperatures such as 1000 ^circC. The SUPREM-IV code was adjusted to enhance the modeling capabilities for high concentration diffusion and implant damage transient enhanced diffusion in two dimensions. The issues involved in the use of local oxidation technology in SOI material and the issues involved in damage annealing of above amorphization dose implantation in SOI material are also discussed in this work. The experimental results from a study of the effects of source/drain annealing on the threshold voltages of 0.125 μm to 50 mu m polysilicon gate length NMOS transistors in bulk and SOI material is also presented. Significantly larger reverse short channel effects due to enhanced diffusion of the channel dopant towards the gate interface are evident for lower temperature annealing. The magnitude of the threshold roll-up is significantly reduced in the SOI devices. This study shows that differences in dopant diffusion during identical processing of bulk and SOI devices can have very large effects on electrical behavior.