Technology Mapping of Lookup Table Based Field Programmable Gate Arrays.

The Field Programmable Gate Array (FPGA) is a very attractive technology for application specific integrated circuit designs due to its advantages of short design cycle and low manufacturing cost for small volume productions. Lookup -table (LUT) based FPGAs lead to many applications from circuit emulation to guided missile control due to its reprogrammability. Technology mapping is a crucial step in the FPGA design process and has strong impact on cost and performance. This dissertation addresses the technology mapping problems of LUT based FPGAs, with focus on three optimization objectives, namely delay minimization, area minimization, and area/delay trade-off. For delay minimization, we give a strong polynomial time depth-optimal algorithm, and generalize it to a delay -optimal algorithm under arbitrary static net-delay models. These are the first provably optimal polynomial time FPGA mapping algorithms for general K-bounded Boolean networks, representing a theoretical breakthrough. We also propose a scheme for incorporating logic resynthesis into technology mapping, which results in better solution quality with less running time compared with previous approaches. Finally, we show that for dynamic delay models, the delay minimization problem is NP-hard, and propose a heuristic to use dynamic delay information in static delay minimization. For area minimization, we give an area-optimal duplication-free mapping algorithm that runs in polynomial time. This algorithm is based on our maximum fanout-free cone decomposition of general Boolean networks, which characterizes the network structure and has many other applications. We also give efficient post-processing algorithms for area minimization, which exploit beneficial logic duplication and matching based global optimization. To further meet the real design requirements, we propose a scheme for area/delay trade-off in technology mapping. By integrating our area and delay minimization efforts through a set of depth relaxation techniques, for each design we are able to produce a spectrum of solutions with smooth area/delay trade-off, hence offering multiple choices to the designers. The algorithms have been implemented as a software package and have been thoroughly tested on both benchmark circuits and real designs. Empirical study shows significant improvements over previous algorithms and systems in terms of both delay and area minimization.