X-Ray Lithography Processing and Reliability of 0.5-0.25 Micron Nmos Devices.

As the device dimensions shrink and the complexity increases, the resolution and the process latitude of the lithography system become more critical, demanding a more aggressive patterning process such as X-ray lithography. For sub-quarter-micron technology, X-ray lithography excels demonstrating very good process latitude and resolution much better than 0.25 mu m. However, for device fabrication it is not only important to demonstrate the high resolution and process latitude of X-ray lithography but also important to integrate the lithography with device processing and to understand the side effects of using X-ray lithography, namely, radiation damage in the device dielectrics. The main result of this dissertation is the study of the radiation damage in the gate oxide of the 0.5-0.25 mu m NMOS devices that were exposed to lithographic X-rays during processing. This objective was achieved by conducting a three-part study: the first part concentrated on developing a sub-micron NMOS process that uses X-ray lithography; the second part concentrated on understanding the oxide behavior under exposure using simple MOS capacitors; and the last part concentrated on studying the damage in the exposed full NMOS devices. The radiation damage observed in the devices was explained in term of a new oxide defect creation model.