Feasibility study, software design, layout and simulation of a twodimensional Fast Fourier Transform machine for use in optical array interferometry
Abstract
The goal of this project was the feasibility study of a particular architecture of a digital signal processing machine operating in real time which could do in a pipeline fashion the computation of the fast Fourier transform (FFT) of a timedomain sampled complex digital data stream. The particular architecture makes use of simple identical processors (called inner product processors) in a linear organization called a systolic array. Through computer simulation the new architecture to compute the FFT with systolic arrays was proved to be viable, and computed the FFT correctly and with the predicted particulars of operation. Integrated circuits to compute the operations expected of the vital node of the systolic architecture were proven feasible, and even with a 2 micron VLSI technology can execute the required operations in the required time. Actual construction of the integrated circuits was successful in one variant (fixed point) and unsuccessful in the other (floating point).
 Publication:

Final Report
 Pub Date:
 August 1994
 Bibcode:
 1994wpi..rept.....B
 Keywords:

 Architecture (Computers);
 Fast Fourier Transformations;
 Feasibility Analysis;
 Microprocessors;
 Sampled Data Systems;
 Signal Processing;
 Systolic Arrays;
 Computerized Simulation;
 Digital Data;
 Interferometry;
 Very Large Scale Integration;
 Optics