A key requirement for achieving high yield multichip modules (MCM's) is assuring that the individual dice are known good devices (KGD). A KGD is defined as a bare die available at the same quality and reliability as the equivalent single chip packaged parts. Integrated circuits (IC's) that are Known Good will function over a specified temperature range, are compatible with the MCM approach utilized, and contain no short-term or long-term reliability hazards. The application of reliability and testability techniques at all levels of MCM development, particularly at the chip level, will maximize MCM yield. Today's testing and qualification requirements, defined by MIL-STD-883 Methods 5008 and 2010, are not capable of assuring KGD as defined above. The development of cost effective requirements for achieving 99.9 percent yields poses a challenge which requires new and novel approaches and better methods for bare die testing, wafer level burn-in, tape automated bonding (TAB), temporary packaging, at-speed device testing at the wafer, die, and MCM level. Also of great importance are the methods for built-in self test (BIST), built-in test (BIT), and boundary scan. New standards in very large scale integration (VLSI) device testing must be developed in order for MCM's to be reliable and economical. Rome Laboratory (RL) has funded a program to address and develop these requirements. The objectives of the RL program are to: research and evaluate current and proposed burn-in, electrical and interconnect test techniques for assuring known good VLSI circuits at wafer and die level; and evaluate various methods of incorporating testability features which will decrease test time and cost. In addition, MCM-level reliability and performance assessment procedures will be evaluated to determine appropriate testing concepts and procedures that will assure the procurement of reliable, cost effective MCM's for DOD/NASA applications. The program consists of two phases: Phase One will be a study phase to evaluate, analyze, trade-off, and select best techniques for test and burn-in of wafers, bare die and MCM's. Phase Two will be a demonstration of a cost effective procedure for assuring high quality/reliable production of MCM's based on the KGD methods developed in Phase One.
- Pub Date:
- October 1994
- Cost Effectiveness;
- Integrated Circuits;
- Tabs (Control Surfaces);
- Very Large Scale Integration;
- Electronics and Electrical Engineering