A bipolar analog front-end integrated circuit for the SDC silicon tracker

A low noise, low power, high bandwidth, radiation hard, silicon bipolar transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker. The IC was designed and tested at LBL and was fabricated using CBIC-U2, 4 GHz f(sub T) complementary bipolar technology. Each channel contains the following functions: low noise preamplification, pulse shaping, and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 micron pitch double-sided silicon strip detector. The chip measures 6.8 mm by 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to four times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a Phi = 10(exp 14) protons/sq cm have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.