CMOS gate array characterization procedures
Abstract
Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.
- Publication:
-
Final Report
- Pub Date:
- September 1993
- Bibcode:
- 1993fcri.rept.....S
- Keywords:
-
- Characterization;
- Chips (Electronics);
- Circuits;
- Cmos;
- Gates (Circuits);
- Radiation Hardening;
- Microprocessors;
- Radiation Dosage;
- Radiation Tolerance;
- Solid-State Physics