The time domain crossbar (TDX): A high speed, high density, FPGA design

As system clock rates of electronic designs steadily increase, the need for high bandwidth communication between designs in the system becomes critical. The time domain crossbar (TDX) provides programmable, high-speed communications bandwidth across the user I/O pins of a VME backplane. The TDX time-multiplexes 20 MHz byte-wide data onto 80 MHz byte-wide data for transmission between boards. A programmable register set allows the user to open and close virtual communication channels by configuring independent data paths between sets of boards. Because each additional TDX board provides another crossbar, the overall system bandwidth increases with the number of TDX boards.