Automated Cell Synthesis of Analog Integrated Circuit Layout Anasyn.

This thesis describes a novel model to automate cell generation for the design of analog integrated circuits and the conclusions about important features that such automation should include. This research represents the first attempt to address this problem by analyzing relevant issues of what constitutes an analog cell and how a technique can be implemented to generate these cells automatically. Our motivation for doing this is the critical limitations to circuit performance which arise from cell design. This thesis defines unique construction properties for the layout of some commonly used analog circuit topologies or cells. This thesis defines the physical layout of analog circuit cells beyond simple geometrical description. Each cell is an independent object that can be interfaced and communicated with. This thesis has extended the concept of an analog cell even further by incorporating synthesis rules into the cell definition. These rules are used to dynamically construct the optimized layout that will satisfy many of the options encountered in actual analog circuit design such as area, matching, tolerance, element rationing and parasitic components. This model can construct complex geometric shapes such as common-centroids, waffles, interdigitated, cascode etc. that are optimized at device level with the precise models for parasitic components. Furthermore, Object-Oriented implementation used in this thesis allow for easy integration of this work into other CAD tools. To demonstrate the feasibility and correctness of the ideas described in this thesis, a CAD tool ANASYN has been written. To test and demonstrate the utility and the performance developed, a variety of test cells have been generated. Data presented clearly demonstrate the uniqueness, flexibility, and precision of the analog circuit layout cells implemented in this research thesis. In addition, one test chip and one design chip have been laid out using cells generated by ANASYN and fabricated at the Defense Advanced Research Project Agency (DARPA) silicon foundry referred to as MOSIS. Data are presented which show good agreement between developed cell models and the circuits actually produced.