Modelling and Experimental Analysis of the Impact of Process-Induced Stress on the Electrical Performance of Gallium Arsenide Mesfets

This study comprises the first analysis of the effects of process-induced stresses on the electrical characteristics of GaAs MESFET's, where an account is taken of the stresses in overlayers a priori. These stresses, or rather the gradients of these stresses, induce a piezoelectric charge distribution in the substrate which alters the electrical characteristics of a working device. The charge distributions were calculated using a finite element approximation, and these distributions were incorporated into a 2-D device simulator to extract the pertinent information on FET performance. Good qualitative agreement was found between experiment and numerical simulation, and this opened up the prospect of further speculative modelling of the effects changing device parameters would have on the electrical characteristics of an FET. This study considered variations in the following device parameters: (a) gate-source separation, (b) gate length, (c) gate height, (d) thickness of the dielectric overlayer, and (e) switching gate orientation from the (011) to the (011) direction. For example it was found that as one varied the parameter T (i.e. the thickness of the dielectric overlayer) from 666A to 2000A, the threshold voltage was at first pushed negatively, but as T increased V_ {rm t} was shifted positively. The subthreshold current slope (STS) displayed similar tendencies. This effect has been seen previously, but this is the first successful modeling of this phenomenon. Clear evidence was presented suggesting that the (011) FET orientation is preferable to the (011) direction. The induced piezoelectric charge in the (011) case is opposite in sign to that of the (011) orientation and acts in such a way as to cause an improvement in V_{ rm t} and STS. The dependence of these electrical characteristics on changes in structural device parameters is greatly improved.