Programmable Optoelectronic Multiprocessors: Design, Performance and CAD Development

This thesis describes the development of Programmable Optoelectronic Multiprocessor (POEM) architectures and systems. POEM systems combine simple electronic processing elements with free-space optical interconnects to implement high-performance, massively-parallel computers. POEM architectures are fundamentally different from architectures used in conventional VLSI systems. Novel system partitioning and processing element design methods have been developed to ensure efficient implementation of POEM architectures with optoelectronic technology. The main contributions of this thesis are: architecture and software design for the POEM prototype built at UCSD; detailed technology design-tradeoff and comparison studies for POEM interconnection networks; and application of the VHSIC Hardware Description Language (VHDL) to the design, simulation, and synthesis of POEM computers. A general-purpose POEM SIMD parallel computer architecture has been designed for symbolic computing applications. A VHDL simulation of this architecture was written to test the POEM hardware running parallel programs prior to prototype fabrication. Detailed performance comparison of this architecture with all-optical computing, based on symbolic substitution, has also been carried out to show that POEMs offer higher computational efficiency. A detailed technological design of a packet-switched POEM multistage interconnection network system has been performed. This design uses optically interconnected stages of K x K electronic switching elements, where K is a variable parameter, called grain-size, that determines the ratio of optics to electronics in the system. A thorough cost and performance comparison between this design and existing VLSI implementations was undertaken to show that the POEM approach offers better scalability and higher performance. The grain-size was optimized, showing that switch sizes of 16 x 16 to 256 x 256 provide maximum performance/cost. The effects of varying architectural and technological parameters on the system performance/cost were also examined. Finally, the basic network architecture was extended to provide hardware support for synchronization services that are required in distributed computing. VHDL simulation and synthesis tools were used to functionally design and test clock-accurate gate-level models of the architectures being considered.