Design and optimization of high voltage lateral DMOS devices using RESURF technology

One of the most promising solutions of the fabrication of switches for high voltage integrated circuits, Metal Oxide Semiconductor, the Lateral Double diffused Metal Oxide Semiconductor transistor (LDMOS) using the RESURF technique is discussed. This device is compatible with the low voltage circuits (CMOS or bipolar or BiCMOS); furthermore the LDMOS RESURF is easy to process, shows a high voltage handling capability and a good isolation. However, two major problems arise when optimizing this device: high on resistance value, and severe sensitivity of the breakdown voltage on technological parameters. To bypass these drawbacks the use of the following is used: shallow implantation to increase the concentration of the drift area between the channel and the drain; semiresistive layer, like SIPOS, deposited on the oxide between the gate and the drain. Numerical analysis shows that the use of both surface doping and the SIPOS technique will greatly improve the on resistance (between 40 and 60 of the On resistance value of the classic LDMOS RESURF). Moreover, an optimum breakdown voltage value can be reached for geometrical and physical parameters compatible with real technological tolerances. Geometrical parameters (channel drain distance, epi thickness and oxide thickness) and physical ones (epi doping, concentration and junction depth of surface doping) are optimized to obtain a breakdown voltage around 400 V. For the validation purpose of these rules, diodes and RESURF transistors using a surface doping technique and a SIPOS layer are fabricated.